The signal window for a 1T1C FeRAM memory cell is tested using a low reference voltage (Signal Distribution reference voltage low—“SD Vref low”) and a high reference voltage (Signal Distribution reference voltage high—“SD Vref high”) and running some write/read patterns. FIG. 1 shows a signal distribution of an FeRAM memory chip and some typical low/high reference voltages for testing (SD Vref high/low). The signal window of an FeRAM memory cell is the difference of the high signal and the low signal of the cell. The minimum signal window for each cell which can be guaranteed by this prior-art test method is the difference between “SD Vref high” and “SD Vref low”.
As shown in FIG. 2, the signal window distribution can show a main distribution which is much higher than the tested minimum signal window. The cells with a signal window higher than the tested window but lower than the main distribution are most likely to fail during the lifetime of the chip. The easiest method to find these cells would be to increase the range of the high/low reference voltage (SD Vref high/low). But this method would lead to a dramatic increase in failcount and thus to a dramatic decrease in yield because even cells having a very good signal window would fail if one of their signals is at the wrong position in the distribution. This method only checks if the low signal of all cells is below some certain reference and the high signal of all cells is above a certain reference voltage.
To find only cells with a small signal window, a test is needed which finds only cells which have a low signal higher than “SW Vref low” (“SW” stands for “Signal Window”) AND a high signal of the same cell which is lower than “SW Vref high”.
In high parallel testing of memory chips the failures are usually compressed to the smallest redundancy and therefore the information about which cell of a certain group of cells was failing the test is lost. The only information available is that at least one cell of the certain group was failing the test. Due to this compression, it is not possible to test for single Cells which are failing both test 1 AND test 2.
For redundancy repair, a certain signal margin has to be applied to find the weak cells in an FeRAM memory. This criteria leads, however, to a certain yield loss, and in the worst case to chips which are sorted out even though they could have been repaired and used. It would be desirable to be able to find weak cells which need repair, without unnecessary yield loss.
It would be desirable to have a signal window test mode for memory cells which is able to find single cells having small signal windows.